Method for preventing transients during switching processes in integrated switching circuits, and an integrated switching circuit

ABSTRACT

In a method for avoiding transients during switching processes in integrated circuits, a module ( 2.1, 2.2, 2.3 ) of the integrated circuit ( 1 ) is switched from a first operating state to a second operating state, a load change occurring. In this case, it is ensured that the occurring quotient of load change and time duration for the transition from the first operating state to the second operating state does not exceed a limit value that is predetermined or can be predetermined in a targeted manner.

Method for avoiding transients during switching processes in integratedcircuits, and an integrated circuit.

The invention relates to a method for avoiding transients duringswitching processes in integrated circuits and to an integrated circuitin which measures are taken to avoid transients.

On account of switching processes, load fluctuations of greater orlesser magnitude occur in integrated circuits (IC). By way of example,load fluctuations are brought about by the occasional activation ordeactivation of partial regions or modules of an IC. Such connectable ordisconnectable modules are being employed more and more in modern ICssince they enable a demand-oriented control of the power consumption ofthe IC. A module is activated only when it is currently needed. For therest of the time, the module is in an operating state with low or nopower consumption. The change between operating states is usuallyperformed by disconnection of the supply voltage or by disconnection orreduction of the clock frequency of the module.

What is disadvantageous in this case is that the switching processesproduce undesirable transients on the supply lines, which can have adisturbing effect on other chip components. The higher the number ofswitchable modules, the greater the difficulties to be expected.So-called “mixed signal” systems, which combine digital and analogassemblies on an IC, are particularly susceptible to the occurrence oftransients.

In order to reduce the harmful influence of transients, it is alreadyknown to protect sensitive components of the chip from the transients bymeans of suitable shielding.

The invention is based on the object of specifying a method which makesit possible to reduce the harmful influence of transients in integratedcircuits. Furthermore, the invention aims to provide an integratedcircuit having low susceptibility to disturbances caused by transients.

The object formulated is achieved by means of the features of theindependent claims 1, 13 and 20. The subclaims relate to advantageousdevelopments and refinements of the invention.

By virtue of the fact that, in accordance with the features of claim 1,it is ensured that the quotient—occurring during the switchingprocess—of load change and time duration for the transition from thefirst operating state to the second operating state does not exceed alimit value that is predetermined or can be predetermined in a targetedmanner, the transient occurring during the switching process is limited.This is based on the fact that the size of the disturbance caused by thetransient is proportional to the quotient of load change and changeovertime duration (i.e. the time duration for the transition between the twooperating states).

According to a first particularly preferred exemplary embodiment of theinvention, the transient suppression is achieved by ensuring, during theswitching process, that the time duration for the transition from thefirst operating state to the second operating state does not fall belowa time limit that is predetermined or can be predetermined in a targetedmanner. This means that an abrupt changeover between the two operatingstates (as is customary in the prior art) is replaced by a gradualincreasing or decreasing of an operating quantity which effects thechange from the first

operating state to the second operating state. In this case, thechangeover time duration may be kept relatively short e.g. in the caseof small load changes (i.e. in the case of a module which exhibits onlya small load difference in the two operating states), whilecorrespondingly longer changeover time durations are to be provided whenlarger load differences occur. In this case, the predetermined timelimit for the changeover time duration may also be made dependent onother influencing quantities, for example on whether other modules inthe chip that are particularly sensitive to transients are active orinactive during the switching process.

In many cases, e.g. in the case of disconnection of a module, thetargeted lengthening of the transition time duration for the switchingprocess is associated with no practical disadvantages.

The transition from the first operating state to the second operatingstate may advantageously be effected in step-by-step or progressivefashion or else in continuous fashion.

A second exemplary embodiment of the method according to the inventionis based on a module subdivided into individually switchable submodules.It is characterized in that the switching of the module from the firstoperating state to the second operating state is carried out bysequential switching, in particular disconnection, of the submodules. Asa result of the sequential switching of individual submodules, insteadof an overall load change, a plurality of smaller load changes arecarried out successively, as a result of which the transient that occursis limited.

In a third exemplary embodiment of the method according to theinvention, the load change occurring during the switching of the modulefrom the first operating state to the second operating state isessentially compensated for by simultaneous supplementary connection ordisconnection of a dummy load. Since the supplementary connection ordisconnection of the dummy load is effected at the same time as theswitching of the module, the switching process as such can be abrupt.The occurrence of transients is prevented here by the fact that theoverall load change occurring during the switching process remainssmall.

Preferably the magnitude of the dummy load is controlled before and/orafter the supplementary connection or disconnection of the dummy load.Controlling the magnitude of the dummy load before switching makes itpossible to use a dummy load for switching processes of differentmodules. Controlling the magnitude of the dummy load after theconnection thereof makes it possible to reduce the overall load, whichnow again has to be effected “slowly”, i.e. taking account of the lowertime limit for changeover processes, since the transient would otherwiseoccur during the disconnection of the dummy load.

One advantageous embodiment variant of the invention is characterized inthat the operating quantity that effects the transition from the firstoperating state to the second operating state is the operating voltageof the module. In this case, e.g. in the first exemplary embodiment ofthe invention, the operating voltage is increased or decreased “slowly”during a switching process.

A further, likewise advantageous embodiment variant of the invention ischaracterized in that the operating quantity is the clock frequency ofthe module. In this case, e.g. in the first exemplary embodiment of theinvention, the operating state of the module is changed by means of a“retarded” transition between the two clock frequencies.

In all the exemplary embodiments of the invention, the two operatingstates considered are preferably the switched-on state and theswitched-off state of the module. Another possibility is for one of thetwo operating states to be a state with a reduced operating voltage orreduced clock frequency.

This may be e.g. a standby state or, given a reduced clock frequency, astate with a reduced computation capacity and power consumption.

Switching processes of individual modules to states with a reduced powerconsumption are of interest particularly in the case of chips in thefield of mobile radio. Since the power consumption of the ICs in mobileradio receivers is subject to strict limitations, it is of particularinterest here to effect “low” clocking of individual modules if only amedium or low computing power is required of them in certain situations.On account of this, the invention enables the disturbing influencesbrought about by transients to be significantly reduced in the case of apower management of modules in a chip.

An IC according to the invention has a means for producing an operatingquantity that effects the transition between the operating states forthe module. In this case, said means ensures, during a switchingprocess, that the time duration for the transition from the firstoperating state to the second operating state does not fall below a timelimit that is predetermined or can be predetermined in a targetedmanner.

Preferably, the means for producing the operating quantity comprises anoperating quantity generator, which_produces a fixed value of theoperating quantity, and an operating quantity modulator, to which thefixed operating quantity value is fed and which can provide, at itsoutput, an operating quantity that can be varied between a firstoperating quantity value, at which the module is in the first operatingstate, and a second operating quantity value, at which the module is inthe second operating state.

Furthermore the integrated circuit preferably has a control means, whichdrives the operating quantity modulator during a switching process. Thetime duration for the transition from the first to the

second operating quantity value can be predetermined in variable fashionby means of the control means. Said time duration may be dependent onthe load change occurring during the switching process and/or dependenton further influencing quantities, such as, for example, the operatingstates of other modules of the IC.

The IC preferably comprises both analog and digital modules. In thiscase, the switchable module considered may also be both an analog and adigital module.

The invention is explained below using exemplary embodiments withreference to the drawing, in which,

FIG. 1 shows a simplified block diagram for elucidating the constructionof a first exemplary embodiment of an IC according to the invention; and

FIG. 2 shows a simplified block diagram for elucidating the constructionof further exemplary embodiments of an IC according to the invention.

Modern ICs comprise a multiplicity of components or modules of differentcomplexity and different construction. In this case, in order to obtainhigher system integration, analog and digital modules are also realizedon one and the same IC. By way of example, an IC may comprise one ormore A/D converters, D/A converters, logic units, memory areas and alsoa microprocessor or a microcontroller as different modules. In the fieldof mobile radio applications, analog radiofrequency components (e.g.mixing stages) are realized together with digital baseband assemblies(e.g. digital filters) on an IC. A further example of IC-integratedmodules is task-specific hardware data paths which execute specificpredetermined computation tasks in sequential logic.

A module in the sense of the invention is thus an essentially autonomousfunctional unit or assembly in an IC which cooperates with othercomponents or further switchable modules of the IC, the module generallyparticipating in specific shared resources such as, for example, thepower supply or clock generation of the IC.

FIG. 1 shows, in a simplified illustration, the construction of such anIC 1 in the form of a block diagram. The IC 1 comprises a centralprocessing unit (CPU) 2 and a plurality of further modules 2.1, 2.2 and2.3. The modules 2.1 to 2.3 perform different, task-specific functionsof the IC 1 and may be realized for example in the form of theabovementioned functional units.

The IC 1 furthermore comprises a clock generating circuit 3, which isconstructed from a clock generator 3.1 and a clock divider 3.2 in theexample illustrated here. The clock generator 3.1 is operated by anexternal oscillating crystal 7. It generates a fixed clock frequencywhich is fed to the clock divider 3.2 via a line 8.

A control circuit 4 is connected both to the clock divider 3.2 and tothe central processing unit 2 via bi-directional data connections 5 and6.

The clock divider 3.2 generates the clock signals for the centralprocessing unit 2 and the diverse modules 2.1, 2.2 and 2.3. The clocklines via which the clock signals are passed to the units and modulesmentioned are designated by the reference symbol 9 (for the CPU 2), 9.1(for the module 2.1), 9.2 (for the module 2.2) and 9.3 (for the module2.3) in FIG. 1.

The circuit illustrated in FIG. 1 functions as follows:

By way of example, the module 2.2 is intended to be switched to anoperating state with a low power consumption on account of low capacityutilization. The possibility of effecting lower clocking of the module2.2 is recognized in the central processing unit 2 and correspondinginformation is sent to the control circuit 4 via the data connection 6.The operating states and clock frequencies of the central processingunit 2 and of all the modules 2.1, 2.2 and 2.3 may be known to thecontrol circuit 4, which may simultaneously be a state monitoringdevice, or are communicated to said control circuit via the dataconnections 6 and 5, respectively. With such system informationoptionally being taken into account, the control circuit 4 instructs theprogrammable frequency divider 3.2 to reduce the clock frequency for themodule 2.2 to a desired target value. This target value may either bedetermined in variable fashion by the central processing unit 2 or befixedly predetermined.

A special case exists when the module 2.2 is intended to bedisconnected. In this case, the target value is 0 Hz.

However, the frequency divider 3.2 does not perform an abrupt change ofthe clock frequency for the module 2.2 to the target value, but rathercarries out a slow transition in the frequency from its original valueto the target value. This may be effected either in a plurality ofdiscrete steps or in continuous fashion. On account of the fact that aspecific, predetermined time duration for the transition is notundershot, the occurrence of transients can be avoided or limited asdesired.

The transition time duration may either be a system-wide fixed timeduration for all the modules 2.1, 2.2 and 2.3 or the time duration maybe determined individually for each module 2.1, 2.2, 2.3. Furthermore,the time duration can be set by the control circuit 4 taking account ofthe type of state change (e.g. switching-on or disconnection) and/or theload change associated with the changeover and, if appropriate, takingaccount of further system parameters which are dependent on the state ofother modules 2.1, 2.2, 2.3.

FIG. 2 diagrammatically shows a second exemplary embodiment of theinvention. The same or functionally comparable parts are identified bythe same reference symbols as in FIG. 1. The essential differencebetween the first exemplary embodiment illustrated in FIG. 1 and thesecond exemplary embodiment illustrated in FIG. 2 is that, in the secondexemplary embodiment the transition of a module 2.1, 2.2 or 2.3 from afirst operating state to a second operating state is effected by achange in the supply voltage of the corresponding module. In thisrespect, the reference symbol 3.1′ designates a circuit for generating asupply voltage and the reference symbol 3.2′ designates a circuit forcontrolling and altering the supply voltage obtained from the circuit3.1′ via the line 8. The reference symbol 10 designates an externalpower source, for example a battery, and the reference symbol 3′designates a circuit for generating the supply voltages for the centralprocessing unit 2 and the modules 2.1, 2.2 and 2.3. The supply voltagelines via which the supply voltages are passed to the modules mentionedare designated by the reference symbols 9′ (for the CPU 2), 9.1′ (forthe module 2.1), 9.2′ (for the module 2.2) and 9.3′ (for the module 2.3)in FIG. 2.

The functioning of the components of the IC 1′ is analogous to thefunctioning of the components of the IC 1. The analogy consists in thefact that operating voltages or operating voltage changes and associatedswitching processes are now considered instead of clock frequencies orclock frequency changes. In order to avoid repetition, reference is madeto the description concerning the

first exemplary embodiment in the sense of this analogy.

A further exemplary embodiment of the invention is likewise explainedwith reference to FIG. 2. The module 2.2 to be switched is supplementedby a dummy load, which is intended to be represented here by thereference symbol 2.3. Unlike in the first or second exemplary embodimentof the invention, the switching process with regard to the module 2.2can now be carried out abruptly. At the same time, the dummy load 2.3 islikewise supplementarily connected abruptly. The dummy load 2.3 isdimensioned such that it precisely compensates for the load changeeffected by the switching of the module 2.2. Since, as a consequence, noor only a very small overall load change is associated with theswitching process, the occurrence of transients is effectivelysuppressed.

The dummy load 2.3 may be of adjustable magnitude, as a result of whichtwo different things are achieved: firstly, it can be used duringswitching processes for different load changes or modules. Secondly, itcan be slowly choked after supplementary connection, as a result ofwhich the overall load—and thus the current consumption—is reduced againin a desired manner.

In a further exemplary embodiment, not specifically illustrated, themodule to be switched is constructively subdivided into a plurality ofsubmodules which are individually switchable. The switching of themodule is carried out in the form of sequential switching of theindividual submodules, so that the module, e.g. during disconnection, isramped down section by section (i.e. submodule by submodule).

It is pointed out that all the exemplary embodiments can be combined. Inother words, it is conceivable for the IC to comprise both functionalelements which are put into different states by means of a protractedswitching process for the operating voltage and to comprise modules

in which operating state changes are brought about by a protractedfrequency change. Furthermore, it is possible to provide abruptswitching processes with supplementary connection or disconnection ofthe dummy load of suitable magnitude or sequential disconnection of amodule subdivided into submodules. With regard to an individual module,too, it is possible, in principle, for a plurality of the possibilitiesmentioned to be realized. In this case, an integrated circuit accordingto the invention comprises e.g. both frequency and voltage controldevices which may be embodied in accordance with the circuits 3 and 3′and are provided with corresponding peripherals 7, 10. Furthermore, thedummy load 2.3 is required if the intention is to realize changeoverswith the participation of a dummy load 2.3.

1. A method for avoiding transients during switching processes inintegrated circuits, having the steps of: switching a module (2.1, 2.2,2.3) of the integrated circuit (1, 1′) from a first operating state to asecond operating state, a load change occurring, and in this caseensuring that the quotient—occurring during the switching process—ofload change and time duration for the transition from the firstoperating state to the second operating state does not exceed a limitvalue that is predetermined or can be predetermined in a targetedmanner.
 2. The method as claimed in claim 1, characterized in that thetime duration for the transition from the first operating state to thesecond operating state does not fall below a time limit that ispredetermined or can be predetermined in a targeted manner.
 3. Themethod as claimed in claim 2, characterized by the step of: controllingthe time duration for the transition from the first operating state tothe second operating state.
 4. The method as claimed in one of claims 1to 3, characterized in that the transition from the first operatingstate to the second operating state is effected in step-by-step fashion.5. The method as claimed in one of claims 1 to 3, characterized in thatthe transition from the first operating state to the second operatingstate is effected in continuous fashion.
 6. The method as claimed in oneof claims 2 to 5, the module being subdivided into individuallyswitchable submodules, characterized in that the switching of the modulefrom the first operating state to the second operating state is carriedout by sequential switching, in particular disconnection, of thesubmodules.
 7. The method as claimed in claim 1, characterized by thestep of: during the switching of the module (2.1, 2.2), simultaneoussupplementary connection or disconnection of a dummy load (2.3), whichessentially compensates for the load change occurring during theswitching of the module (2.1, 2.2).
 8. The method as claimed in claim 7,characterized in that the magnitude of the dummy load (2.3) iscontrolled before and/or after the supplementary connection ordisconnection of the dummy load (2.3).
 9. The method as claimed in oneof the preceding claims, characterized in that the transition from thefirst operating state to the second operating state is produced bychanging the operating voltage of the module (2.1, 2.2, 2.3).
 10. Themethod as claimed in one of claims 1 to 8, characterized in that thetransition from the first operating state to the second operating stateis produced by changing the clock frequency of the module (2.1, 2.2,2.3).
 11. The method as claimed in one of the preceding claims,characterized in that the two operating states are the switched-on stateand the switched-off state.
 12. The method as claimed in one of claims 1to 10, characterized in that the two operating states are theswitched-on state and a state with a reduced value of an operatingquantity, in particular clock frequency or supply voltage, of themodule.
 13. An integrated circuit having: at least one module (2.1, 2.2,2.3) that can be switched selectively between a first operating stateand a second operating state, a change between the operating statesbeing associated with a load change, a means (3, 3′) for producing anoperating quantity that effects the transition between the operatingstates for the module (2.1, 2.2, 2.3), the means (3, 3′) for producingthe operating quantity ensuring, during a switching process, that thetime duration for the transition from the first operating state to thesecond operating state does not fall below a time limit that ispredetermined or can be predetermined in a targeted manner.
 14. Theintegrated circuit as claimed in claim 13, characterized in that theoperating quantity is the operating voltage of the module (2.1, 2.2,2.3).
 15. The integrated circuit as claimed in claim 13, characterizedin that the operating quantity is the clock frequency of the module(2.1, 2.2, 2.3).
 16. The integrated circuit as claimed in claims 13 to15, characterized in that the means (3, 3′) for producing the operatingquantity comprises: an operating quantity generator (3.1, 3.1′) forproducing a fixed value of the operating quantity, and an operatingquantity modulator (3.2, 3.2′), to which the fixed operating quantityvalue is fed and which can provide, at its output, an operating quantitythat can be varied between a first operating quantity value, at whichthe module (2.1, 2.2, 2.3) is in the first operating state, and a secondoperating quantity value, at which the module (2.1, 2.2, 2.3) is in thesecond operating state.
 17. The integrated circuit as claimed in claim16, characterized by a control means (4), which drives the operatingquantity modulator (3.2, 3.2′) during a switching process.
 18. Theintegrated circuit as claimed in claim 17, characterized in that thecontrol means (4) is designed to predetermine the time duration for thetransition from the first to the second operating quantity value. 19.The integrated circuit as claimed in claims 13 and 16, characterized inthat the operating quantity is the clock frequency, and in that theoperating quantity modulator (3.2) is a clock divider circuit withdifferent clock divider factors.
 20. An integrated circuit having: atleast one module (2.1, 2.2) that can be switched selectively between afirst operating state and a second operating state, a change between theoperating states being associated with a load change, means forswitching the module (2.1, 2.2) from the first operating state to thesecond operating state, and means for simultaneous supplementaryconnection or disconnection of a dummy load (2.3), which essentiallycompensates for the load change occurring during the switching of themodule.
 21. The integrated circuit as claimed in claim 20, characterizedin that the magnitude of the dummy load (2.3) is adjustable.
 22. Theintegrated circuit as claimed in one of claims 13 to 21, characterizedin that the integrated circuit (1, 1′) comprises analog and digitalmodules.
 23. The integrated circuit as claimed in one of claims 13 to22, characterized in that the integrated circuit (1, 1′) is a chip of amobile station of a mobile radio system.